The increasing of higher level of integration within electrical integrated circuit (IC) leads to both higher data rates and larger number of IC interconnections. Today, the inherent signal speed of IC is increased to 3 GHz, and shortly it will be reached to over 10 GHz. The number of pin connection is also increased, with single IC requiring close to 2000 interconnection (i.e. single processor), and shortly it will be increased to over 5000. Simultaneously achieving higher data rates and higher interconnect densities within the higher level of packaging, covering from die-level packaging to chip-to-chip (hereafter chip indicates the die with package) interconnection on the printed circuit board (PCB), will be increasingly difficult as the IC technologies continue to evolve increasing the signal speed and interconnection number.
With increasing of the signal speed and interconnection number within the IC, low-cost high-level packaging and related interconnection technology after post packaging are highly desirable to make available in consumer level. The packaging technology especially for single chip package (also mentioned as packaged-chip in the text) is improved to tackle the signal speed and pin connections. Ball grid array (BGA), chip scale package (CSP) etc. for IC package are developed accommodating required pin connections and the signal speeds, and it can accommodate the on-chip (inside the chip) speed. However, when it comes to the case of chip-to-chip (off-chip) connection on the PCB, the transition from thin film technology (which is IC and packaging technology) to the thick film technology of the PCB is a primarily dramatic transition. This is not only in terms of the technology but also in terms of interconnection density achievable on the single layer. With increasing of on-chip signal speed, the off-chip signal speed also increases. This off-chip electrical signal creates noises such as reflection caused by poor shapes of electrical interconnects, connecting the inter chip, or the influence of the cross-talk. In addition, the high-speed signal creates also high frequency electromagnetic waves from the electric interconnect to adversely affects the peripheral circuits. To reduce this reflection loss transmission line is to be properly designed with the proper characteristic impedance through out the inter-chip signal line with minimal discontinuities. To suppress the electromagnetic affect on the neighboring circuit, proper signal line and shielding in the PCB is to be designed. In the case of high speed off-chip interconnects especially over 3 GHz where line length is long, both reducing reflection loss and also suppressing electromagnetic interference are practically challenging in some extent, and are not cost-effective to implement by using of conventional PCB technology. Today's off-chip electrical interconnects are being implementing by lowering the signal speed at the level where conventional PCB technology is used and no such problems are occurred. In this case, the fully integration technology within IC in other words, the intra chip signal speed is not fully utilized.
FIG. 1 shows the schematic representing the conventional chip-to-chip interconnection on the conventional PCB 100. Here, chip 120 (for example processor) is connected with chip 130 (for example 3) by multilayered electrical signal lines 110 in the PCB 1. FIG. 2 shows the schematic representing the conventional BGA (ball grid array) and CSP (chip-scaled package) based packaging for high-speed single chip package (for example processor). In both type of packagings, die 122 and die 132 are attached with the ceramic or polymer substrate 124 and 134, respectively, containing the matrix of pins 126 and 136. Outside pins 128 and 138, located at the bottom-side of chip package (in both packaging cases) connect with the PCB, whereas topside of the package is connected with the heat sink to dissipate heat from the die. Both types of packages provide closer proximity of signal as on-chip. The fidelity of signal occurred due to the conventional electrical off-chip interconnections 110 through multiplayer PCB 100. It is highly desirable having the board-level electrical signal connection for high-speed off-chip connection, which could be compatible with existing IC package such as BGA, CSP etc., and also could be employed conventional PCB technologies.
To alleviate the problems such as cross talk, electromagnetic interference etc. usually occur in the high speed electrical interconnects, electrical signal lines in off-chip interconnects are partially replaced by the optical interconnects using the optical fiber or optical waveguide as the media. This is because the optical signal eliminates EMI problem and also reduces the generation of loss for even longer signal line interconnects. Many papers and patents applications (both international and US) disclose concerning optical interconnects in off-chip connection. One typical example is disclosed in Toshiyoshi et al., IEEE/OSA Journal of Lightwave Technology, Vol.17, No.1, pp.19-25(1999). In this report, chip-to-chip interconnection based on wavelength division multiplexing (WDM) technique is proposed. Free-space optical interconnection technique between IC chips are employed to transfer and receiving the optical signal using of micro-electro-mechanical system (MEMS) device. The proposed concept is similar to conventional WDM technique, frequently used in optical communication. This technique could increase the capacity per channel. However, if this technique is used in off-chip interconnections where chip-to-chip distance is few centimeters, this technique will be make the whole interconnection bulky, and could not be used in practical application where existing chip package and conventional PCB technology are frequently used.
This WDM technique may have no problem for use in the board-to-board interconnection where distances are few meters. However, in an application where existing chip with package such as BGA and CSP are used, the use of this free-space optic concept makes the interconnects more bulky, and miniaturization is difficult to achieve. Furthermore, free space optics concept is also not friendly to implement in the electronics systems such as desktop computer and video-gaming system, which are generally operated in dusty environment, and the deterioration of optical signal transmission/receiver may happen due to poor signal in long run system use. For the electronics system where miniaturization and the cost are the issues, it would be highly desirable to design the optical interconnects which could compatible existing chip package.
In conventional optical interconnects, where free-space optics techniques and/or Z-direction of the chip is used for transmitting the optical signal from transmitter to receiver, most of the time, cooling of the electronics chips are not being considered in most of the inventions, disclosed so far. With increasing of the on-chip speed, chip power consumption is also increasing. For the case of the electronics chip, dissipating large amount of heat, additional cooling system is necessary and conventionally, z-direction is used for cooling purpose. Today's optical interconnects where, chip's z-direction, is used for transmitting/receiving the optical signal, in such optical interconnects technique, cooling means can't be implemented and thereby, such optical interconnects are impractical for high speed off-chip interconnects.
U.S. Pat. No. 6,434,308 B1 (inventor: Trezza) discloses a connector system for the optical transceiver for interconnecting the chips through an array of emitters and detectors. In this connector system, the fiber bundles are used as a media to transmit and receive the optical signals for off-chip communication. In the disclosed patents, chip with package system aren't considered to make interconnects. The main drawbacks of this connector system is that additional interface board including packaging may necessary to make inerchip communication in chip with package level communication. Furthermore, this way of communication using of the fiber bundles prevents the system from miniaturization and not suitable for the electronics system, especially for off-chip communication. This connector system may suitable for the optical interconnects, especially board-to-board interconnects.
U.S. Pat. No. 6,411,418 B1 (inventors: Deri et al.) discloses architecture for multiprocessors interconnection using of WDM technique. Here, independent channels on different optical wavelengths are simultaneously broadcast to many nodes over a star coupler. No packaging scheme is described compatible for the chip package. This scheme may increase the bandwidth and latency and can't be applicable for the off-chip interconnects for the application like electronics system where chip with package level interconnects is concerned. Additional interface board including packaging scheme is necessary to implement this architecture.
As explained above, conventional electronics interconnect for off-chip communication has the drawbacks that integration technology of IC is not fully utilized, and also that exiting conventional electrical interconnects have the limitation of maintaining available on-chip signal speed. Today, the electrical interconnects among more than single chip are done at the speed limit where the cross talk, electromagnetic interference could be eliminated and this speed limit is below the speed available in on-chip level. With increasing on-chip signal speed, it is necessary to adopt interconnect technology which is compatible with today's chip-package and also could be easily implemented in the practical system.
Optical interconnects could eliminate the problems, that arises in high speed electrical off-chip interconnects. However, optical interconnects technology so far disclosed have also drawbacks that an interconnect system are not compatible with the chip (with package) level interconnects. For implementing the conventional optical interconnects into the practical application, whole chip-package technology is required to be developed or have different package technology compatible for the disclosed optical interconnects. Furthermore, the conventional interconnect technology is not friendly for manufacturing, which would be costly and far from the practical application. In addition, today's optical interconnects doesn't consider chip's cooling means. It is highly desirable to have an optical interconnects technique which is compatible to the today's chip-package and considers the chip cooling.